Data receiver gain enhancement

ABSTRACT

An improved data receiver gain enhancement is obtained in circuit by having a V/I converter and an amplifier stage, by placing a passive filter between in converter and amplifier stage. Amplification of certain parts of the signal, more than other parts can be obtained, depending on the characteristics of the filter.

[0001] This invention relates to gain enhancement, particularly to enhancement of a data receiver circuit for high speed data reception.

BACKGROUND OF THE INVENTION

[0002] Amplification is used to amplify incoming signals of variable (small) amplitude to rail-to-rail logic signals. However, variation in signal se can occur, as by losses in the signal path. As a result, the amplified signal can vary in strength.

SUMMARY OF THE PRESENT INVENTION

[0003] As stated above, due to various reasons, the input signal can vary in strength, and so the amplified signal varies in strength. In many applications, typical input signals at 400 Mbits/S (2.5 ns bit cell time) have an amplitude of 200 mV, with occasional smaller pulses of <110.mV. Ideally the receiver would always produce full swing output signals with a constant delay, independent of input signal amplitude. By placing a passive filter between the V/I converter and the inverting amplifier stage, it is possible to amplify certain frequencies within the signal more than others, depending on the characteristics of the filter. This enables compensation for losses earlier in the signal path. Thus a device for enhancement of data receiver gain comprises of V/I converter, an amplifier and a passive filter placed between the amplifier and the V/I converter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004]FIG. 1 illustrates an existing circuit;

[0005]FIG. 2 illustrates the circuitry of an inverter in FIG. 1;

[0006]FIG. 3 illustrates a circuit incorporating the present invention;

[0007]FIG. 4 shows a schematic model for the existing circuit;

[0008]FIG. 5 shows a schematic model for circuit embodying the invention;

[0009]FIG. 6 is a plot of pulse responses;

[0010]FIG. 7 illustrates a gain increase.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0011] In the circuit in FIG. 1, a first stage, a transconductance amplifier (V/I convertor) converts the input voltage V_(in) to a current I1; this is represented by the current source 30. The output impedance of an inverter inv2, 14, translates I1 again to a voltage V2, driving an amplifier stage inv1, 10. inv1, 10, is a CMOS inverter consisting of a PMOS and an NMOS transistor. The circuit of inv1 and inv2 is illustrated in FIG. 2.

[0012] inv2, 14 is an exact copy of inv1, 10, but with the input and output terminals connected together. Because of this feedback inv2, 14, will act as DC voltage source with an impedance determined by the transconductances of its constituting PMOS and NMOS transistors. Since inv2, 14, is matched to inv1, 10, the DC output level of inv2, 14 will be at the optimal operating point for inv1, 10, that is where inv1, 10, has its maximum gain. This configuration is capable of amplification at very high frequencies, up to several hundreds of MHz. The configuration is used in many existing devices.

[0013] By placing a passive filter between the V/I converter and the inv1 amplifier stage it becomes possible to amplify or attenuate certain frequencies within the signal more than others, depending on the characteristics of the filter. This way it becomes possible to compensate for losses earlier in the signal path or to apply any other correction of the frequency transfer characteristic.

[0014] In the particular embodiment illustrated in FIG. 3, a high pass filter is chosen in order to promote the transitions of the data signal. In FIG. 3 items common with FIG. 2 use the same reference numerals. The filter comprises capacitor 20 and resistors 22 and 24.

[0015] Implementation of the high-pass filter with passive components provides a very flexible solution, enabling an optimal placement of the filter pole and zero in order to accommodate to the channel transfer characteristics.

[0016] The filter is optionally made with components available in an IC process. Gain improvement of a factor of 2 (6 dB) above a certain frequency, an example 100 MHz, can easily be achieved.

[0017]FIGS. 4 and 5 show schematic models for the previously known (FIG. 4) and the new circuit in accordance with the invention (FIG. 5). Both have a current source, 30, representing the input signal. These sources 30, J-X and J-Y, produce the same signals.

[0018] The pulse responses are plotted in FIG. 6. At small levels of the input signal the output signal amplitude is considerably increased—the increased signal being seen at the dotted line—as seen in FIG. 6A. The relative increase becomes smaller for larger signal amplitudes, as in FIG. 6B and FIG. 6C, due to the non-linear characteristic of the inverter amplifier. This is desirable, as it is observed tat the filter works for small input signals.

[0019] In the frequency domain, FIG. 7 shows a greater than 6 dB gain increase at beyond 100 MHz signal frequencies, up to >1 GHz for this particular filter.

[0020] Although in the above embodiment, a high pass filter is shown, a low pass filter used for de-emphasis and noise reduction is also possible.

[0021] Numerous other embodiments may be envisaged without departing from the spirit or scope of the invention. For example, a NAND gate may be used in place of the inverter. Further, different types of filters are useful with the invention; a passive filter was chosen in the preferred embodiment due to its simplicity and adequacy for the design. 

What is claimed is:
 1. A semiconductor device having a known frequency transfer characteristic comprising: a filter for receiving a first input signal and a second input signal and for providing a filtered signal; a first port for receiving a current forming the first input signal, a first inverter electrically coupled to the filter for receiving the filtered signal; and, a second inverter having an input terminal and an output terminal electrically coupled to the input terminal and electrically coupled to the filter and for providing the second input signal thereto.
 2. A semiconductor device according to claim 1 comprising: a V/I converter electrically coupled to the port for providing the current.
 3. A semiconductor device according to claim 2 wherein the filter is a passive filter.
 4. A semiconductor device according to claim 3 wherein device forms pan of a data receiver for gain enhancement.
 5. A semiconductor device according to claim 1 wherein the inverter comprises a NAND gate with the inputs coupled together.
 6. A semiconductor device according to claim 1 wherein the inverter comprises a NOR gate with the inputs coupled together.
 7. A semiconductor device according to claim 1 comprising the filter is low-pass.
 8. A semiconductor device according to claim 1 wherein the filter is high pass.
 9. A semiconductor device comprising: a V/I converter; a first inverter; an electrical connection between an output of said converter and an input of said first inverter; a second inverter, having its input and output terminals connected; first connection from said electrical connection to said second inverter; a second connection, spaced form said first connection, to said second inverter; a passive filter between said V/I converter and said first inverter, said passive filter comprising a firs(resistor in said first connection, a second resistor in said second connection, and a capacitor in said electrical connection, between said first and second connections.
 10. A method of enhancing data receiver gain, comprising a passive filter disposed between a V/I converter and an inverter wherein a second inverter having its input and output conductors coupled together is used to stabilise the circuit transfer function. 